Many electronic systems, including audio and communications systems, require generation of a high quality, agile signal source for use as, for example, a local oscillator, sample clock, frequency modulator, or the like. For this purpose, such systems typically include signal or frequency synthesizers, which can be tuned within a few microseconds over the entire frequency band that is available for a given output signal.
One traditional type of frequency synthesizer is a phase locked loop (“PLL”), which is a feedback control system that generates an output signal having a phase that is related to the phase of an input reference signal. During operation of a common PLL, the input reference signal is provided to a phase frequency detector, which generates a voltage signal that is provided to a low pass filter (“LPF”) to improve loop stability and eliminate any reference spurs in the voltage signal. An output of the low pass filter is used to drive a voltage controlled oscillator (“VCO”), which generates an output signal with an oscillation frequency that is controlled by the input voltage. The PLL circuit further includes a feedback path or loop, and the VCO output signal is provided to a frequency or loop divider on this path. The divider (also referred to herein as an “N divider”) divides the frequency of the VCO output signal by an integer value N that is selected so that the divided frequency is exactly the same as the reference frequency. An output of the N divider is provided to the phase frequency detector as a second input, along with the fixed reference signal. The phase frequency detector compares the phase and frequencies of the two input signals and outputs a voltage proportional to a difference in phase and/or frequency between the two input signals. This voltage is then used to drive the VCO, thereby completing the feedback loop of the PLL. In this manner, the output of the VCO can be locked to the phase of the reference signal and the reference frequency, or an N multiple thereof.
There are several factors that affect the performance of a PLL system and make it difficult to design an ideal PLL that has, for example, narrow channel spacing and a broad range of output frequencies. As a result, the traditional PLL system, also known as an “integer N PLL,” typically has several drawbacks, including, for example, slow settling times and high in-band noise levels that are difficult to filter out. For example, the magnitude of the integer value, N, of the loop divider impacts the noise performance of the feedback loop because any phase noise or spurious noise in the reference frequency will appear in the loop output with its original magnitude multiplied by N. As a result, the noise level increases substantially when the N value is large. However, a large N value is required in order to achieve high frequency resolution and to accommodate VCO output signal frequencies that are large compared to the reference frequency (e.g., a large multiple thereof).
As another example, the frequency of the reference signal determines the frequency resolution, or step size, of the PLL, such that the lower the reference frequency, the higher the frequency resolution and number of frequency channels. However, there is a tradeoff between frequency resolution and settling time (also referred to as “lock time” or “frequency switching time”), which is the amount of time it takes a PLL to change to a new output frequency (e.g., during frequency hopping or when changing channels). While a smaller settling time is preferred, so that the PLL settles on the new frequency as quickly as possible, this requires a higher reference frequency. As will be appreciated, the bandwidth of the loop filter is typically five to ten percent of the reference frequency and has an inverse effect on the settling time of the PLL (i.e. the wider the bandwidth of the loop filter, the faster the settling time). However, a higher reference frequency means lower frequency resolution for the PLL, which is not desirable. And a wider bandwidth on the loop filter is not desirable because this can degrade loop stability and may not effectively reduce spurious emissions produced by the reference frequency and its harmonics.
To resolve some of the performance challenges in the integer N PLL, a “fractional N” PLL may be used. This PLL system uses non-integer frequency division to provide a finer frequency resolution than the more traditional PLL, or lower output noise for an identical resolution. However, the fractional N PLL still suffers from spurious tones in the output signal, as will be appreciated.
Another existing type of frequency synthesizer is a direct digital synthesizer (“DDS”), which is a sampled data system that creates periodic digital signals, or arbitrary waveforms, from a single, fixed-frequency reference clock. A DDS can be used to synthesize a frequency lower than that of its input clock or reference signal. Advantages of the DDS over the traditional PLL include better frequency agility, improved phase noise, and precise control of the output phase across frequency switching transitions. However, traditional DDS systems also have certain drawbacks, including, for example, the difficulty of filtering out higher order harmonics in the output signal due to aliasing and a higher noise floor at large frequency offsets. As will be appreciated, in order to achieve good signal quality, the signals produced by a frequency synthesizer must have very little phase or spurious noise, or a high spectral purity. In a DDS circuit, the spectral purity of the output signal is primarily determined by a digital-to-analog converter (“DAC”) coupled in series with the DDS to generate an analog output signal based on the digital signal produced by the DDS. However, even an ideal N-bit DAC will produce harmonics with an amplitude that is dependent on the ratio of the output frequency to the clock frequency, thereby contributing to the higher noise floor of the conventional DDS. Further, the higher order harmonics produced by the DAC fold back into the Nyquist bandwidth, making them unfilterable.
As an attempt to resolve some of the above performance challenges in traditional frequency synthesizers, U.S. Pat. No. 4,965,533 describes a hybrid frequency synthesizing system 100 that includes a DDS circuit 102 for generating the input reference signal of an integer N PLL 104, as shown in FIG. 1. Due to inclusion of the DDS circuit 102, the hybrid system 100 provides a higher frequency resolution and frequency range than the traditional PLL, as well as a faster settling time. More specifically, as shown in FIG. 1, a stable signal source 106 is applied as an input to a DDS 108, and a digital output of the DDS 108 is applied to an N-bit digital-to-analog converter (“DAC”) 110 included in the DDS circuit 102 to convert the digital output of the DDS 108 into an analog signal. A bandpass filter (“BPF”) 112 is included in the path between the DDS circuit 102 and the integer N PLL 104 to suppress or eliminate wideband spurious noise from the output signal of the DDS circuit 102, so that a magnitude of the spurs are not multiplied by the value N of an N divider 114 included in a feedback loop 116 the PLL 104. As will be appreciated, the integer N PLL 104 includes a phase frequency detector (“PFD”) 118, a low pass filter (“LPF”) 120, and a voltage controlled oscillator (“VCO”) 122, all connected in series, as is conventional. As shown in FIG. 1, the filtered DDS output signal is input to the PFD 118 as the input reference signal of the PLL 104. By using the DDS circuit 102 as the reference to the PLL 104, the reference frequency can be varied in extremely small steps (i.e. with a very fine frequency resolution), while the PLL 104 can have a relatively large frequency step size and therefore, a wide permissible bandwidth for the loop filter 120, thereby providing a faster settling time for the PLL 104.
However, the existing DDS driven PLL hybrid system 100 still has certain drawbacks that fall short of providing a practical, high performance solution. For example, the system 100 is expensive to manufacture and consumes a large amount of power, due at least in part to the N-bit DAC 102. Further, the prior art system 100 is susceptible to spurious tones because the N-bit DAC 110 is a weighted Nyquist digital-to-analog converter with a spurious free dynamic range that limits the spurious performance of the DDS system 102. As will be appreciated, while any remaining spurious signals in the output signal received from the BPF 112 can be filtered out by the PLL 104 if outside the bandwidth of the PLL 104, any spurs that are within this bandwidth are multiplied by the PLL 104. While, in theory, the quantization noise introduced by the DDS 108 is expected to spread uniformly over the Nyquist bandwidth, practical applications have shown that this is not the case even when using an N-bit DAC. Instead, the quantization noise is highly signal dependent and may be concentrated at multiples of the output frequency. As a result, even an ideal multi-bit DAC will produce harmonics in the output signal, which are ultimately fed to the PLL 104 being driven by the DDS system 102.